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3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility
Rev. C pASIC 2 HIGHLIGHTS
(R)
QL2003
Ultimate Verilog/VHDL Silicon Solution
-Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance -Design tools produce fast, efficient Verilog/VHDL synthesis
Speed, Density, Low Cost and Flexibility in One Device
... 3,000 usable ASIC gates, 118 I/O pins
-16-bit counter speeds exceeding 200 MHz -3,000 usable ASIC gates, 5,000 usable PLD gates, 118 I/Os -3-layer metal ViaLink(R) process for small die sizes -100% routable and pin-out maintainable
3
pASIC 2
Advanced Logic Cell and I/O Capabilities
-Complex functions (up to 16 inputs) in a single logic cell -High synthesis gate utilization from logic cell fragments -Full IEEE Standard JTAG boundary scan capability -Individually-controlled input/feedback registers and OEs on all I/O pins
Other Important Family Features
-3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2003 Block Diagram
192 Logic Cells
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QL2003
PRODUCT SUMMARY The QL2003 is a 3,000 usable ASIC gate, 5,000 usable PLD gate member of the pASIC 2 family of FPGAs. pASIC 2 FPGAs employ a unique combination of architecture, technology, and software tools to provide high speed, high usable density, low price, and flexibility in the same devices. The flexibility and speed make pASIC 2 devices an efficient and high performance silicon solution for designs described using HDLs such as Verilog and VHDL, as well as schematics. The QL2003 contains 192 logic cells. With 118 maximum I/Os, the QL2003 is available in 84-PLCC, 100-pin TQFP and 144-pin TQFP packages. Software support for the complete pASIC families, including the QL2003, is available through three basic packages. The turnkey QuickWorks(R) package provides the most complete FPGA software solution from design entry to logic synthesis (by Synplicity, Inc.), to place and route, to simulation. The QuickToolsTM and QuickChipTM packages provide a solution for designers who use Cadence, Mentor, Synopsys, Viewlogic, Veribest, or other thirdparty tools for design entry, synthesis, or simulation. FEATURES
Total of 118 I/O Pins
- 110 bidirectional input/output pins, PCI-compliant at 5.0V in -1/-2 speed grades - 4 high-drive input-only pins - 4 high-drive input/distributed network pins
Four Low-Skew (less than 0.5ns) Distributed Networks
- Two array networks available to logic cell flip-flop clock, set, and reset - each driven by an input-only pin - Two global clock/control networks available to F1 logic input, and logic cell flip-flop clock, set, reset; input and I/O register clock, reset, enable; and output enable controls - each driven by an input-only pin, or any input or I/O pin, or any logic cell output or I/O cell feedback
High Performance
- Input + logic cell + output delays under 6 ns - Datapath speeds exceeding 225 MHz - Counter speeds over 200 MHz
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QL2003
PINOUT DIAGRAM
84-PIN PLCC
3
pASIC 2
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QL2003
PINOUT DIAGRAMS PIN # 76 PIN # 1 100-PIN TQFP
pASIC QL2003-1PF100C
PIN # 51 PIN # 26 144-PIN TQFP PIN # 1 PIN # 109
pASIC QL2003-1PF144C
PIN # 73 PIN # 37 3-8
QL2003
100 and 144 TQFP Pinout Table
144 100 TQFP TQFP 1 2 2 NC 3 3 4 4 5 NC 6 5 7 NC 8 6 9 NC 10 7 11 NC 12 NC 13 8 14 NC 15 9 16 10 17 11 18 12 19 13 20 14 21 15 22 16 23 17 24 18 25 NC 26 19 27 NC 28 20 29 21
Function I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O GND I/O I ACLK / I VCC I GCLK / I VCC I/O I/O I/O I/O I/O I/O I/O
144 100 TQFP TQFP 30 NC 31 NC 32 22 33 NC 34 23 35 NC 36 24 37 25 38 26 39 27 40 28 41 29 42 NC 43 30 44 31 45 NC 46 32 47 33 48 NC 49 34 50 35 51 36 52 NC 53 37 54 38 55 39 56 40 57 41 58 42
Function GND I/O I/O I/O I/O I/O I/O I/O TDI I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O GND I/O I/O I/O VCC
144 100 TQFP TQFP 59 NC 60 43 61 44 62 45 63 NC 64 NC 65 46 66 NC 67 NC 68 NC 69 47 70 48 71 49 72 50 73 51 74 52 75 53 76 54 77 55 78 NC 79 NC 80 NC 81 56 82 NC 83 57 84 NC 85 58 86 NC 87 59
Function I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O TRSTB TMS I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O GND
144 100 TQFP TQFP 88 60 89 61 90 62 91 63 92 64 93 65 94 66 95 67 96 NC NC 68 97 NC 98 69 99 NC 100 70 101 71 102 NC 103 NC 104 72 105 NC 106 73 107 74 108 75 109 76 110 77 111 78 112 79 113 80 114 NC 115 81
Function I/O I ACLK / I VCC I GCLK / I VCC I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O TCK STM I/O I/O I/O VCC I/O
144 100 TQFP TQFP 116 82 117 83 118 NC 119 84 120 NC 121 NC 122 85 123 NC 124 86 125 87 126 88 127 89 128 90 129 91 130 92 131 NC 132 93 133 NC 134 94 135 NC 136 NC 137 95 138 NC 139 96 140 97 141 98 142 99 143 100 144 1
Function I/O I/O I/O I/O I/O I/O GND I/O I/O I/O GND I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O TDO I/O
3
pASIC 2
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QL2003
PIN DESCRIPTIONS
Pin TDI TRSTB TMS TCK TDO STM I/ACLK I/GCLK I I/O VCC GND Function Test Data In for JTAG Active low Reset for JTAG Test Mode Select for JTAG Test Clock for JTAG Test data out for JTAG Special Test Mode High-drive input and/or array network driver High-drive input and/or global network driver High-drive input Input/Output pin Power supply pin Ground pin Description Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold LOW during normal operation. Connect to ground if not used for JTAG. Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold HIGH or LOW during normal operation. Connect to VCC or ground if not used for JTAG. Output that must be left unconnected if not used for JTAG. Must be grounded during normal operation. Can be configured as either or both. Can be configured as either or both. Use for input signals with high fanout. Can be configured as an input and/or output. Connect to 3.3V supply. Connect to ground.
ORDERING INFORMATION
QL 2003 - 1 PF100 C
QuickLogic pASIC device Operating Range C = Commercial I = Industrial
pASIC 2 device part number Package Code PL84 = 84-pin PLCC PF100 = 100-pin TQFP PF144 = 144-pin TQFP
Speed Grade X = quick 0 = fast 1 = faster 2 = fastest
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QL2003
ABSOLUTE MAXIMUM RATINGS
Supply Voltage .................... -0.5 to 7.0V Input Voltage ............. -0.5 to VCC +0.5V ESD Pad Protection ................... 2000V DC Input Current ...................... 20 mA Latch-up Immunity ................... 200 mA Storage Temperature................ -65C to + 150C Lead Temperature ................................ 300C
5 Volt OPERATING RANGE
Symbol VCC TA TC K Parameter Supply Voltage Ambient Temperature Case Temperature -X Speed Grade Delay Factor -0 Speed Grade -1 Speed Grade -2 Speed Grade Industrial Min Max 4.5 5.5 -40 85 0.4 0.4 0.4 0.4 2.75 2.00 1.61 1.35 Commercial Min Max 4.75 5.25 0 70 0.46 0.46 0.46 0.46 2.55 1.85 1.50 1.25 Unit V C C
3
pASIC 2
DC CHARACTERISTICS over 5V operating range
Symbol VIH VIL VOH VOL II IOZ CI IOS ICC Notes: [1] [2] [3] [4] -24 mA IOH and 24 mA IOL apply only to -1/-2 commercial grade devices. These speed grades are also PCI-compliant. All other devices have -16 mA IOH and 16 mA IOL specifications. Capacitance is sample tested only. Only one output at a time. Duration should not exceed 30 seconds. For -0/-1/-2 commercial grade devices only. Maximum ICC is 20 mA for -X commercial grade devices and 15mA for all industrial grade devices. For AC conditions, contact QuickLogic customer engineering. Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input Leakage Current 3-State Output Leakage Current Input Capacitance [2] Output Short Circuit Current [3] D.C. Supply Current [4] Conditions Min 2.0 3.7 2.4 VCC-0.1 0.45 0.1 10 10 10 -120 210 10 Max 0.8 IOH = -4 mA IOH = -24 mA/-16 mA [1] IOH = -10 A IOL = 24 mA/16 mA [1] IOL = 10 A VI = VCC or GND VI = VCC or GND VO = GND VO = VCC VI, VIO = VCC or GND Unit V V V V V V V A A pF mA mA mA
-10 -10 -15 40 2 (typ)
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QL2003
3.3 Volt OPERATING RANGE
Symbol VCC TA K Parameter Supply Voltage Ambient Temperature -0 Speed Grade Delay Factor -1 Speed Grade -2 Speed Grade Industrial Min Max 3.0 3.6 -40 85 0.56 2.74 0.56 2.21 0.56 1.85 Commercial Min Max 3.0 3.6 0 70 0.61 2.65 0.61 2.14 0.61 1.79 Unit V C
DC CHARACTERISTICS over 3.3V operating range
Symbol VIH VIL VOH VOL IIH II IOZ CI IOS ICC Notes: [5] [6] [7] Capacitance is sample tested only. Only one output at a time. Duration should not exceed 30 seconds. For commercial grade devices only. Maximum ICC is 5 mA for all industrial grade devices. For AC conditions, contact QuickLogic customer engineering. Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input High Current Sink (for tolerance to 5V devices) Input Leakage Current 3-State Output Leakage Current Input Capacitance [5] Output Short Circuit Current [6] D.C. Supply Current [7] Conditions Min 2.0 2.4 VCC-0.1 0.4 0.1 12 -10 -10 -10 25 0.5 (typ) 10 10 10 -70 130 3 Max 0.8 IOH = -2.4 mA IOH = -10 A IOL = 4 mA IOL = 10 A 5.5V > VI > VCC VI = VCC or GND VI = VCC or GND VO = GND VO = VCC VI, VIO = VCC or GND Unit V V V V V V mA A A pF mA mA mA
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QL2003
AC CHARACTERISTICS at VCC = 5V, TA = 25C (K = 1.00) Propagation delays depend on routing, fanout, load capacitance, supply voltage, junction temperature, and process variation. The AC Characteristics are a design guide to provide initial timing estimates at nominal conditions. Worst case estimates are obtained when nominal propagation delays are multiplied by the appropriate Delay Factor, K, as specified in the Delay Factor table (Operating Range). The QuickChip/QuickTools/QuickWorks software incorporates data sheet AC Characteristics into the design database for precise path analysis or simulation results following place and route. Logic Cells
Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Parameter Combinatorial Delay [9] Setup Time [9] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width 1 1.4 1.8 0.0 0.8 2.0 2.0 1.4 1.2 1.9 1.8 Propagation Delays (ns) Fanout [8] 2 3 4 1.7 2.0 2.3 1.8 1.8 1.8 0.0 0.0 0.0 1.1 1.4 1.7 2.0 2.0 2.0 2.0 2.0 2.0 1.7 2.0 2.3 1.5 1.8 2.1 1.9 1.9 1.9 1.8 1.8 1.8
3
pASIC 2
8 3.5 1.8 0.0 2.9 2.0 2.0 3.5 3.3 1.9 1.8
Input-Only Cells
Symbol tIN tINI tISU tIH tlCLK tlRST tlESU tlEH Notes: [8] Stated timing for worst case Propagation Delay over process variation at VCC=5.0V and TA=25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. These limits are derived from a representative selection of the slowest paths through the pASIC 2 logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design. Parameter High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time 1 2.5 2.6 4.8 0.0 0.9 0.8 4.1 0.0 Propagation Delays (ns) Fanout [8] 2 3 4 8 12 2.6 2.6 2.7 3.5 4.6 2.7 2.7 2.8 3.6 4.7 4.8 4.8 4.8 4.8 4.8 0.0 0.0 0.0 0.0 0.0 1.0 1.0 1.1 1.9 3.0 0.9 0.9 1.0 1.8 2.9 4.1 4.1 4.1 4.1 4.1 0.0 0.0 0.0 0.0 0.0
24 5.8 5.9 4.8 0.0 4.2 4.1 4.1 0.0
[9]
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QL2003
Clock Cells
Symbol tACK tGCKP tGCKB Parameter Array Clock Delay Global Clock Pin Delay Global Clock Buffer Delay 1 2.2 1.2 1.5 Propagation Delays (ns) Loads per Half Column [10] 2 3 4 8 10 2.2 2.3 2.4 2.5 2.6 1.2 1.2 1.2 1.2 1.2 1.6 1.6 1.7 1.8 1.9
13 1.2 2.0
I/O Cells
Symbol tI/O tISU tIH tlOCLK tlORST tlESU tlEH Parameter Input Delay (bidirectional pad) Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time 1 1.8 4.8 0.0 0.8 0.7 4.1 0.0 Propagation Delays (ns) Fanout [8] 2 3 4 8 2.1 2.4 2.7 3.9 4.8 4.8 4.8 4.8 0.0 0.0 0.0 0.0 1.1 1.4 1.7 2.9 1.0 1.3 1.6 2.8 4.1 4.1 4.1 4.1 0.0 0.0 0.0 0.0 Propagation Delays (ns) Output Load Capacitance (pF) 50 75 100 3.0 3.6 4.1 3.3 3.9 4.5 2.6 3.1 3.7 3.3 4.1 4.9
10 4.6 4.8 0.0 3.6 3.5 4.1 0.0
Symbol tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Notes:
Parameter Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-State [11] Output Delay Low to Tri-State [11] 30 2.6 2.8 2.1 2.6 2.9 3.3
150 5.2 5.7 4.8 6.5
[10] The array distributed networks consist of 48 half columns and the global distributed networks consist of 52 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to 10 loads per half column. The global clock has up to 13 loads per half column. [11] The following loads are used for tPXZ:
tPHZ 1K 5 pF 1K tPLZ 5 pF
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